6.5080 - Multicore Programming Upd

Recognizing that locks have fundamental limits (blocking, priority inversion, and convoying), 6.5080 introduces non-blocking synchronization. Students implement a lock-free stack using operations. They learn the ABA problem (a pointer changes from A to B and back to A, fooling the CAS) and solve it with tagged pointers or double-word CAS.

Before writing a single parallel loop, 6.5080 insists on understanding the hardware. Multicore processors do not provide a “perfectly simultaneous” view of memory. Instead, each core possesses private L1 and L2 caches, a shared L3 cache, and the main DRAM. This hierarchy introduces the problem of . The course covers the MESI (Modified, Exclusive, Shared, Invalid) protocol extensively. A student learns why two threads incrementing the same shared variable from different cores can miss each other’s updates, leading to lost counts. 6.5080 multicore programming

More subtly, 6.5080 introduces —specifically, the Total Store Order (TSO) used by x86 and the weaker Relaxed Memory model of ARM and PowerPC. Through hands-on experiments, students discover that without memory barriers, a thread may read a stale value even after another thread has visibly written a new one. This module’s key takeaway is that correctness in multicore programming is not merely about avoiding race conditions in logic; it is about controlling the order of memory operations as observed by different cores. Before writing a single parallel loop, 6

6.5080 Institution: (Contextualized as an advanced graduate/upper-level undergraduate course in Computer Science) Date: April 13, 2026 This hierarchy introduces the problem of

6.5080 Multicore Programming is not merely a course about APIs; it is a course about disciplined thinking under nondeterminism. It replaces the comforting linearity of sequential code with a rigorous engineering discipline. The student emerges with three lifelong reflexes: (1) distrust shared mutable state by default; (2) prefer composable, high-level patterns (fork-join, pipelines) over raw low-level locks; and (3) measure before optimizing—your intuition about parallelism is almost always wrong. As processor architectures move toward hybrid designs (performance cores + efficiency cores, chiplets, and near-memory computing), the principles taught in 6.5080 remain foundational. The free lunch may be over, but with the skills from this course, the engineer can cook their own parallel feast.